confs.bib

@inproceedings{deliparaschos_fast_2005,
  address = {Catania, Sicily},
  title = {A fast digital fuzzy logic controller: {FPGA} design and implementation},
  volume = {1},
  shorttitle = {A fast digital fuzzy logic controller},
  url = {http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=1612530&abstractAccess=no&userType=inst},
  abstract = {This paper describes an improved approach to design a Takagi-Sugeno zero-order type fast parameterized digital fuzzy logic controller ({DFLC}) processing only the active rules (rules that give a non-null contribution for a given input data set), at high frequency of operation, without significant increase in hardware complexity. To achieve this goal, an improved method of designing the fuzzy controller model is proposed that significantly reduces the time required to process the active rules and effectively increases the input data processing rate. The {DFLC} discussed in this paper achieves an internal core processing speed of at least 200 {MHz}, featuring two 8-bit inputs and one 12-bit output, with up to seven trapezoidal shape membership functions per input and a rule base of up to 49 rules. The proposed architecture was implemented in a field programmable gate array ({FPGA}) chip with the use of a very high-speed integrated-circuits hardware-description-language ({VHDL}) and advanced synthesis and place and route tools},
  booktitle = {10th {IEEE} Conf. on Emerging Technologies and Factory Automation ({IEEE} {ETFA}'05)},
  author = {Deliparaschos, K. M. and Nenedakis, F. I. and Tzafestas, S. G.},
  month = sep,
  year = {2005},
  keywords = {controllers, data processing, {DFLC}, digital fuzzy logic controller, field programmable gate array chip, field programmable gate arrays, {FPGA} design, fuzzy control, fuzzy logic, hardware-description-language, hardware description languages, logic design, trapezoidal shape membership function, very high-speed integrated-circuit, very high speed integrated circuits, {VHDL}},
  pages = {259--262}
}
@inproceedings{michail_k._ai-based_2013,
  address = {Platania-Chania, Crete, Greece},
  title = {Ai-based low computational power actuator/sensor fault  detection applied on a maglev suspension},
  author = {Michail, K., Deliparaschos, K. M. and Tzafestas, S. G. and Zolotas, A. C.},
  month = jun,
  year = {2013},
  file = {K Michail et al. - 2013 - Ai-based low computational power actuatorsensor f.pdf:/Users/delk/Library/Application Support/Zotero/Profiles/5tof7bfa.default/zotero/storage/EDQBJPHW/K Michail et al. - 2013 - Ai-based low computational power actuatorsensor f.pdf:application/pdf}
}
@inproceedings{deliparaschos_parameterized_2007,
  address = {Angers, France},
  title = {A parameterized genetic algorithm ip core design and implementation.},
  isbn = {978-972-8865-82-5},
  url = {http://dblp.uni-trier.de/db/conf/icinco/icinco2007-icso.html#DeliparaschosDT07},
  abstract = {Genetic Algorithm ({GA}) is a directed random search technique working on a population of solutions and based on natural selection. However, its convergence to the optimum may be very slow for complex optimization problems, especially when the {GA} is software implemented, making it difficult to be used in real time applications. In this paper a parameterized {GA} {IP} is designed and implemented on hardware, achieving impressive time–speedups when compared to its software version. The parameterization stands for the number of population individuals and their bit resolution, the bit resolution of each individual’s fitness, the number of elite genes in each generation, the crossover and mutation methods, the maximum number of generations, the mutation probability and its bit resolution. The proposed architecture is implemented in a field programmable gate array chip ({FPGA}) with the use of a very high-speed integrated circuits hardware description language ({VHDL}) and advanced synthesis and place and route tools. The {GA} discussed in this work achieves a frequency rate of 92 {MHz} and is evaluated using the Traveling Salesman Problem as well as several benchmarking functions.},
  booktitle = {Int. Conf. on Informatics in Control, Automation and Robot ({ICINCO}'10)},
  author = {Deliparaschos, K. M. and Doyamis, G. C. and Tzafestas, S. G.},
  month = may,
  year = {2007},
  keywords = {dblp},
  pages = {417--423}
}
@inproceedings{deliparaschos_autonomous_2007,
  title = {Autonomous {SoC} for fuzzy robot path tracking},
  url = {http://dl.acm.org/citation.cfm?id=1831968},
  booktitle = {Proceedings of the European Control Conference},
  author = {Deliparaschos, K. M., Moustris, G. P. and Tzafestas, S. G.},
  month = jul,
  year = {2007}
}
@inproceedings{deliparaschos_design_2009,
  address = {Patras, Greece},
  title = {Design paradigms of intelligent control systems on a chip},
  url = {www.pacet.gr/pacet2009/doc/papers/paper-27.pdf},
  booktitle = {Panhellenic Conf. on Electronics \& Telecommunications ({PACET}’09)},
  author = {Deliparaschos, K. M. and Tzafestas, S. G.},
  month = mar,
  year = {2009}
}
@inproceedings{deliparaschos_optimised_2013,
  address = {Nice, France},
  title = {Optimised sensor selection for control: a hardware-in-the-loop realization on {FPGA} for an {EMS} system},
  author = {Deliparaschos, K. M., Michail, K., Tzafestas, S. G. and Zolotas, A. C.},
  month = oct,
  year = {2013},
  file = {Deliparaschos et al. - 2013 - Optimised sensor selection for control a hardware.pdf:/Users/delk/Library/Application Support/Zotero/Profiles/5tof7bfa.default/zotero/storage/GN3DPUX5/Deliparaschos et al. - 2013 - Optimised sensor selection for control a hardware.pdf:application/pdf}
}
@inproceedings{deliparaschos_reduced_2014,
  address = {Athens},
  title = {Reduced power expenditure in the minimum latency transmission scheduling problem},
  booktitle = {International Symposium on Communications, Control, and Signal Processing ({ISCCSP}'14)},
  author = {Deliparaschos, K. M., Charalambous, T. and Christodoulides, P. and Klerides, E.},
  month = may,
  year = {2014},
  file = {Deliparaschos et al. - 2014 - Reduced power expenditure in the minimum latency t.pdf:/Users/delk/Library/Application Support/Zotero/Profiles/5tof7bfa.default/zotero/storage/83MIW46S/Deliparaschos et al. - 2014 - Reduced power expenditure in the minimum latency t.pdf:application/pdf}
}
@inproceedings{michail_sensor_2012,
  title = {Sensor fault detection with low computational cost: A proposed neural network-based control scheme},
  shorttitle = {Sensor fault detection with low computational cost},
  doi = {10.1109/ETFA.2012.6489628},
  abstract = {The paper describes a low computational power method for detecting sensor faults. A typical fault detection unit for multiple sensor fault detection with modelbased approaches, requires a bank of estimators. The estimators can be either observer or artificial intelligence based. The proposed control scheme uses an artificial intelligence approach for the development of the fault detection unit abbreviated as ‘i-{FD}’. In contrast with the bank-estimators approach the proposed i-{FD} unit is using only one estimator for multiple sensor fault detection. The efficacy of the scheme is tested on an Electro-Magnetic Suspension ({EMS}) system and compared with a bank of Kalman estimators in simulation environment.},
  booktitle = {2012 {IEEE} 17th Conference on Emerging Technologies Factory Automation ({ETFA})},
  author = {Michail, K. and Deliparaschos, K. M.},
  year = {2012},
  pages = {1--6}
}
@inproceedings{moustris_tracking_2009,
  address = {Budapest, Hungary},
  title = {Tracking control using the strip-wise affine transformation: An experimental {SoC} design},
  url = {http://www.researchgate.net/publication/221719500_Tracking_Control_Using_the_Strip-wise_Affine_Transformation_An_Experimental_SoC_Design},
  abstract = {This paper presents the analysis and application of the strip-wise affine map to the path following task for autonomous non-holonomic mobile robots. The mapping was implemented on a Spartan 3-1500 {FPGA} board with the use of {VHDL} and advanced {EDA} tools and was used in field experiments on a Khepera {II} differential robot. A fully parameterized {DFLC} previously published by the author has been tailored accordingly for the needs of this design implementation. Experiments were performed using a calibrated camera and a video tracking algorithm in order to extract the actual robot’s path, compare it to the odometry solution and analyze the tracker’s performance.},
  booktitle = {European Control Conf. ({ECC}'09)},
  author = {Moustris, G. and Deliparaschos, K. M.},
  month = aug,
  year = {2009},
  file = {Moustris and Deliparaschos - 2009 - Tracking control using the strip-wise affine trans.pdf:/Users/delk/Library/Application Support/Zotero/Profiles/5tof7bfa.default/zotero/storage/2RQ65NXJ/Moustris and Deliparaschos - 2009 - Tracking control using the strip-wise affine trans.pdf:application/pdf}
}
@inproceedings{deliparaschos_model-based_2015,
  address = {Toremolinos, Spain},
  title = {A model-based embedded control hardware/software co-design approach for optimized sensor selection of industrial systems},
  doi = {10.1109/MED.2015.7158858},
  abstract = {In this work, a Field Programmable Gate Array (FPGA)-based embedded software platform coupled with a software-based plant, forming a Hardware-In-the-Loop (HIL), is used to validate a systematic sensor selection framework. The systematic sensor selection framework combines multi-objective optimization, Linear-Quadratic-Gaussian (LQG) control, and the nonlinear model of a maglev suspension. The physical process that represents the suspension plant is realized in a high-level system modeling environment, while the LQG controller is implemented on an FPGA. FPGAs allow to rapidly evaluate algorithms and test designs under real-world scenarios avoiding heavy time penalty associated with Hardware Description Language (HDL) simulators. Moreover, the HIL technique implemented shows a significant speed-up in the required execution time when compared to the software-based model.},
  booktitle = {2015 23th {Mediterranean} {Conference} on {Control} and {Automation} ({MED})},
  author = {Deliparaschos, K.M. and Michail, K. and Tzafestas, S.G. and Zolotas, A.C.},
  month = jun,
  year = {2015},
  keywords = {Analytical models, control engineering computing, Control systems, electromagnetic suspension, embedded control, embedded systems, field programmable gate array-based embedded software platform, field programmable gate arrays, FPGA, FPGA design, FPGA-In-the-Loop, hardware description languages, hardware description language simulators, Hardware design languages, hardware-in-the-loop, hardware-software codesign, HDL, high-level system modeling environment, HIL, HIL technique, industrial systems, linear quadratic Gaussian control, linear-quadratic-Gaussian control, LQG, maglev, maglev suspension, magnetic levitation, magnetic variables control, Mathematical model, MATLAB, model-based embedded control hardware-software codesign approach, multiobjective optimization, nonlinear model, observer-based controller, optimisation, optimized sensor selection, Sensor selection, software-based model, suspension plant, systematic sensor selection framework},
  pages = {889--894},
  file = {IEEE Xplore Abstract Record:/Users/delk/Library/Application Support/Zotero/Profiles/5tof7bfa.default/zotero/storage/WIKKTIIE/articleDetails.html:text/html}
}
@inproceedings{deliparaschos_issue_2017,
	title = {On the issue of {LQG} embedded control realization in a {Maglev} system},
	doi = {10.1109/MED.2017.7984311},
	abstract = {Sensor selection in control design receives substantial interest in the last few years. We disseminate work on Field Programmable Gate Array (FPGA)-based embedded software platform validating a systematic sensor selection framework and target efficient FPGA resource allocation. Sensor selection combines multi-objective optimization, Linear-Quadratic-Gaussian (LQG) control, applied to a Maglev suspension. The nonlinear Maglev model is realized on software platform forming a Hardware-in-the-loop (HIL) as an economic and reliable validation platform for the design setup. The LQG controller was modeled in fixed point, described in Verilog Hardware Description Language (HDL) and tied up with an ethernet core to form an FPGA-in-the-loop system prior to logic synthesis and FPGA place and route. The results illustrate efficient FPGA resource allocation level pertinent to extending to a core sensor fault tolerant scheme.},
	booktitle = {2017 25th {Mediterranean} {Conference} on {Control} and {Automation} ({MED})},
	author = {Deliparaschos, K. M. and Michail, K. and Zolotas, A.},
	month = jul,
	year = {2017},
	keywords = {field programmable gate array, logic synthesis, logic design, control design, Control systems, embedded systems, field programmable gate arrays, magnetic levitation, multiobjective optimization, resource allocation, control engineering computing, Hardware design languages, hardware-in-the-loop, HDL, HIL, linear quadratic Gaussian control, linear-quadratic-Gaussian control, maglev suspension, magnetic variables control, Mathematical model, systematic sensor selection framework, hardware description languages, control system synthesis, Energy management, Environmental management, FPGA resource allocation, FPGA-in-the-loop system, Field programmable gate arrays, LQG embedded control realization, Robot sensing systems, Verilog hardware description language, core sensor fault tolerant scheme, embedded software platform, ethernet core, fault tolerant control, nonlinear maglev model, railway engineering, sensor selection, software platform},
	pages = {1379--1384},
	file = {IEEE Xplore Abstract Record:/Volumes/Evo SD/Dropbox/Libraries/Zotero Library/storage/6JKIS5AZ/7984311.html:text/html}
}

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